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74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Rev. 01 -- 20 January 2009 Product data sheet 1. General description The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry. The 74AUP1T1326 is designed for logic-level translation applications and combines the functions of the 74AUP1G32 and 74AUP1G126. The buffer/line driver is controlled by two output enable Schmitt trigger inputs (1OE and 2OE) through an OR-gate. The output enable inputs accept standard input signals and are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The output of the OR-gate is also available at output 1Y. The output enable inputs (1OE and 2OE) switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH. Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are referenced to VCC(A) and pins A and 2Y are referenced to VCC(B). A logic LOW on both output enable pins causes the output 2Y to assume a high-impedance OFF-state. The device ensures low static and dynamic power consumption and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the outputs, preventing any damaging backflow current through the device when it is powered down. 2. Features I Wide supply voltage range: N VCC(A): 1.1 V to 3.6 V; VCC(B): 1.1 V to 3.6 V. I High noise immunity I Complies with JEDEC standards: N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 2A exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 0.9 A (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages up to 3.6 V NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state I I I I Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1T1326GT -40 C to +85 C XSON8 Description Version plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 x 1.95 x 0.5 mm Type number 4. Marking Table 2. Marking Marking code p31 Type number 74AUP1T1326GT 5. Functional diagram 1OE 5 Rpd 7 1Y 2OE 6 Rpd VCC(A) A 2 VCC(B) 8 2Y 001aaj293 Rpd = Internal pull-down resistor. Fig 1. Logic symbol 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 2 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 6. Pinning information 6.1 Pinning 74AUP1T1326 VCC(B) 1 8 2Y A 2 7 1Y VCC(A) 3 6 2OE GND 4 5 1OE 001aaj294 Transparent top view Fig 2. Pin configuration SOT833-1 (XSON8) 6.2 Pin description Table 3. Symbol VCC(B) A VCC(A) GND 1OE 2OE 1Y 2Y Pin description Pin 1 2 3 4 5 6 7 8 Description supply voltage B data input supply voltage A ground (0 V) output enable input (Schmitt trigger input) output enable input (Schmitt trigger input) data output data output 7. Functional description Table 4. Input 1OE L X X H H [1] Function table[1] Output 2OE L H H X X A X L H L H 1Y L H H H H 2Y Z L H L H H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 3 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC(A) VCC(B) IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage A supply voltage B input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions Min -0.5 -0.5 Max +4.6 +4.6 +4.6 -50 +4.6 20 50 +150 250 Unit V V mA V mA V mA mA mA C mW VI < 0 V [1] -50 -0.5 -0.5 -50 -65 [2] [1] [2] VO > VCCO or VO < 0 V Active mode and Power-down mode VO = 0 V to VCCO Tamb = -40 C to +85 C [3] - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with an output pin. For XSON8 package: above 45 C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC(A) VCC(B) VI VO Tamb t/V Recommended operating conditions Parameter supply voltage A supply voltage B input voltage output voltage ambient temperature input transition rise and fall rate input A; VCCI = 1.1 V to 3.6 V input nOE; VCCI = 1.1 V to 3.6 V [1] [2] VCCO is the supply voltage associated with an output pin. VCCI is the supply voltage associated with an input pin. [2] [2] [1] Conditions Min 1.1 1.1 0 0 -40 - Max 3.6 3.6 3.6 VCCO +85 200 30 Unit V V V V C ns/V ms/V 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 4 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C VIH HIGH-level input A; input voltage V CCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VIL LOW-level input A; input voltage V CCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIL or VI or VI = VT+ or VT- IO = -20 A; VCCO = 1.1 V to 3.6 V IO = -1.1 mA; VCCO = 1.1 V IO = -1.7 mA; VCCO = 1.4 V IO = -3 mA; VCCO = 1.65 V IO = -2.3 mA; VCCO = 2.3 V IO = -4.0 mA; VCCO = 2.3 V IO = -2.7 mA; VCCO = 3.0 V IO = -6.0 mA; VCCO = 3.0 V VOL LOW-level output voltage VI = VIL or VI or VI = VT+ or VT- IO = 20 A; VCCO = 1.1 V to 3.6 V IO = 1.1 mA; VCCO = 1.1 V IO = 1.7 mA; VCCO = 1.4 V IO = 3.0 mA; VCCO = 1.65 V IO = 2.3 mA; VCCO = 2.3 V IO = 4.0 mA; VCCO = 2.3 V IO = 2.7 mA; VCCO = 3.0 V IO = 6.0 mA; VCCO = 3.0 V II input leakage current OFF-state output current input A; VI = 0 V to 3.6 V; VCCI = 1.1 V to 3.6 V output 2Y; VI = VIH or VIL; VO = 0 V to 3.6 V; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V [1] [2] [2] [1][3] [1][3] Conditions Min 25 C Typ Max -40 C to +85 C Min Max Unit 0.65VCCI 1.6 2.0 VCCO - 0.1 0.825 1.05 1.2 1.97 2.0 2.67 2.48 - - 0.35VCCI 0.7 0.9 0.10 0.275 0.35 0.45 0.33 0.40 0.33 0.40 0.1 0.65VCCI 1.6 2.0 VCCO - 0.1 0.825 1.05 1.2 1.97 2.0 2.67 2.48 - 0.35VCCI 0.7 0.9 0.10 0.275 0.35 0.45 0.33 0.40 0.33 0.40 0.5 V V V V V V V V V V V V V V V V V V V V V V A [2] IOZ - - 0.1 - 0.5 A 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 5 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Table 7. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOFF power-off leakage current Conditions Min 1Y; VCC(A) = 0 V; VO = 0 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V A, 2Y; VCC(B) = 0 V; VI or VO = 0 V to 3.6 V; VCC(A) = 1.1 V to 3.6 V IOFF additional power-off leakage current 1Y; VCC(A) = 0 V to 0.2 V; VO = 0 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V A, 2Y; VCC(B) = 0 V to 0.2 V; VI or VO = 0 V to 3.6 V; VCC(A) = 1.1 V to 3.6 V VI = 0 V or VCC(A); IO = 0 A VCC(A) = 1.1 V to 3.6 V; VCC(B) = 0 V to 3.6 V VI = 0 V or VCC(B); IO = 0 A VCC(A) = VCC(B) = 1.1 V to 3.6 V VCC(A) = 1.71 V; VCC(B) = 2.6 V ICC additional supply current nOE; VCC(A) = VCC(B) = 3.3 V; VI = VCC(A) - 0.6 V A; VCC(A) = VCC(B) = 3.3 V; VI = VCC(B) - 0.6 V; A; VI = GND to 3.6 V; nOE = GND; VCC(A) = VCC(B) = 1.1 V to 3.6 V Rpd CI pull-down resistance input capacitance input A; VI = 0 V or VCCI; VCCI = 1.1 V to 3.6 V input nOE; VI = 0 V or VCCI; VCCI = 1.1 V to 3.6 V CO output capacitance 1Y; VO = GND; VCCO = 0 V 2Y enabled; VO = GND; VCCO = 0 V 2Y disabled; VCCO = 0 V to 3.6 V; VO = GND or VCCO [1] [2] [3] [4] VCCI is the supply voltage associated with the input pin. VCCO is the supply voltage associated with the output pin. For VCCI values not specified in the data sheet: minimum VIH = 0.7 x VCCI and maximum VIL = 0.3 x VCCI. To show ICC remains very low when the input-disable feature is enabled. [1] [4] [1] [1] 25 C Typ Max 0.2 - -40 C to +85 C Min Max 0.5 Unit A - - 0.2 - 0.5 A - - 0.2 - 0.6 A - - 0.2 - 0.6 A ICC(A) supply current A supply current B - - 0.5 - 0.9 A ICC(B) - - 0.5 350 40 40 - - 0.9 500 50 50 1 A A A A A 151 - 281 0.9 0.8 1.7 1.7 1.5 428 - 150 - 435 - k pF pF pF pF pF [1] [2] [2] [2] 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 6 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter CL = 5 pF tpd propagation delay A to 2Y; see Figure 3 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V nOE to 1Y; see Figure 3 VCC(A) = 1.1 V to 1.3 V VCC(A) = 1.4 V to 1.6 V VCC(A) = 1.65 V to 1.95 V VCC(A) = 2.3 V to 2.7 V VCC(A) = 3.0 V to 3.6 V CL = 10 pF tpd propagation delay A to 2Y; see Figure 3 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V nOE to 1Y; see Figure 3 VCC(A) = 1.1 V to 1.3 V VCC(A) = 1.4 V to 1.6 V VCC(A) = 1.65 V to 1.95 V VCC(A) = 2.3 V to 2.7 V VCC(A) = 3.0 V to 3.6 V 3.7 3.1 2.9 2.5 2.3 6.4 4.7 4.0 3.4 3.1 10.8 6.8 5.6 4.6 4.1 3.4 2.8 2.5 2.2 2.1 11.1 7.2 6.1 4.9 4.5 ns ns ns ns ns [2] [2] Conditions Min 25 C Typ[1] Max -40 C to +85 C Min Max Unit 3.0 2.4 1.9 1.5 1.2 3.4 2.8 2.4 2.2 1.9 5.4 3.8 3.1 2.3 2.1 5.6 4.2 3.5 2.9 2.6 9.5 5.7 4.5 3.4 3.0 9.3 5.9 4.9 3.9 3.4 2.7 2.1 1.7 1.3 1.0 3.2 2.6 2.2 2.0 1.8 9.7 6.1 5.0 3.8 3.3 9.5 6.3 5.3 4.1 3.7 ns ns ns ns ns ns ns ns ns ns 3.4 2.7 2.3 1.8 1.6 6.2 4.4 3.6 2.8 2.6 11.0 6.6 5.3 4.1 3.8 3.0 2.4 2.0 1.5 1.3 11.4 7.1 5.8 4.5 4.2 ns ns ns ns ns 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 7 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter CL = 15 pF tpd propagation delay A to 2Y; see Figure 3 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V nOE to 1Y; see Figure 3 VCC(A) = 1.1 V to 1.3 V VCC(A) = 1.4 V to 1.6 V VCC(A) = 1.65 V to 1.95 V VCC(A) = 2.3 V to 2.7 V VCC(A) = 3.0 V to 3.6 V CL = 30 pF tpd propagation delay A to 2Y; see Figure 3 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V nOE to 1Y; see Figure 3 VCC(A) = 1.1 V to 1.3 V VCC(A) = 1.4 V to 1.6 V VCC(A) = 1.65 V to 1.95 V VCC(A) = 2.3 V to 2.7 V VCC(A) = 3.0 V to 3.6 V CL = 5 pF; VCC(A) = 1.1 V to 1.3 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V [4] [3] [2] [2] Conditions Min 25 C Typ[1] Max -40 C to +85 C Min Max Unit 3.8 3.2 2.7 2.2 1.8 4.2 3.6 3.1 2.8 2.5 6.9 4.9 4.0 3.2 2.9 7.2 5.2 4.5 3.8 3.5 12.5 7.5 6.0 4.8 4.4 12.4 7.6 6.3 5.3 4.8 3.4 2.8 2.3 1.8 1.6 3.8 3.3 2.7 2.5 2.3 12.9 8.1 6.5 5.3 4.8 12.7 8.2 6.9 5.6 5.2 ns ns ns ns ns ns ns ns ns ns 4.8 4.0 3.5 2.7 2.5 5.1 4.3 4.0 3.4 3.3 9.0 6.3 5.1 4.2 3.9 9.2 6.6 5.6 4.7 4.4 16.6 9.8 7.8 6.2 5.9 16.4 9.9 8.1 6.7 6.2 4.2 3.4 3.0 2.4 2.3 4.6 3.8 3.5 3.0 3.0 17.3 10.6 8.6 6.8 6.4 17.1 10.8 8.9 7.2 6.7 ns ns ns ns ns ns ns ns ns ns 3.4 2.8 3.4 2.8 8.7 7.0 7.1 6.1 20.0 15.6 15.2 13.5 3.2 2.5 3.2 2.5 20.3 15.8 15.5 13.9 ns ns ns ns 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 8 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter CL = 5 pF; VCC(A) = 1.4 V to 1.6 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V CL = 5 pF; VCC(A) = 1.65 V to 1.95 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V CL = 5 pF; VCC(A) = 2.3 V to 2.7 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [4] [3] [4] [3] [4] [3] Conditions Min 25 C Typ[1] Max -40 C to +85 C Min Max Unit 3.4 2.8 2.4 3.4 2.8 2.4 7.8 6.1 5.4 6.3 5.3 5.4 16.6 12.2 10.7 11.8 10.1 9.9 3.1 2.5 2.1 3.1 2.5 2.1 17.1 12.6 11.1 12.3 10.7 10.5 ns ns ns ns ns ns 3.4 2.8 2.4 2.2 3.4 2.8 2.4 2.2 7.4 5.6 4.9 4.4 6.0 5.0 5.1 4.3 15.6 11.2 9.7 8.2 10.8 9.1 8.9 7.8 3.1 2.5 2.1 1.9 3.1 2.5 2.1 1.9 16.0 11.5 10.1 8.8 11.2 9.6 9.4 8.4 ns ns ns ns ns ns ns ns 3.4 2.8 2.4 2.2 1.9 3.4 2.8 2.4 2.2 1.9 6.8 5.0 4.3 3.7 3.6 5.5 4.5 4.6 3.9 4.4 14.6 10.1 8.7 7.2 6.8 9.8 8.1 7.9 6.8 7.3 3.1 2.5 2.1 1.9 1.6 3.1 2.5 2.1 1.9 1.6 14.9 10.4 9.0 7.7 7.3 10.1 8.5 8.3 7.3 7.7 ns ns ns ns ns ns ns ns ns ns 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 9 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter CL = 5 pF; VCC(A) = 3.0 V to 3.6 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V CL = 10 pF; VCC(A) = 1.1 V to 1.3 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V CL = 10 pF; VCC(A) = 1.4 V to 1.6 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V CL = 10 pF; VCC(A) = 1.65 V to 1.95 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V [3] [4] [3] [4] [3] [4] [3] Conditions Min 25 C Typ[1] Max -40 C to +85 C Min Max Unit 3.4 2.8 2.4 2.2 1.9 3.4 2.8 2.4 2.2 1.9 6.5 4.8 4.1 3.4 3.2 5.3 4.3 4.4 3.7 4.2 14.2 9.7 8.2 6.7 6.3 9.3 7.7 7.4 6.4 6.9 3.1 2.5 2.1 1.9 1.6 3.1 2.5 2.1 1.9 1.6 14.4 9.9 8.5 7.2 6.8 9.7 8.0 7.9 6.8 7.2 ns ns ns ns ns ns ns ns ns ns 3.7 3.1 3.7 3.1 9.9 8.0 8.5 7.3 22.9 17.8 18.0 16.0 3.3 2.8 3.3 2.8 23.1 18.1 18.3 16.4 ns ns ns ns 3.7 3.1 2.9 3.7 3.1 2.9 8.8 6.9 6.1 7.6 6.4 6.7 18.8 13.8 12.2 14.0 11.9 12.0 3.3 2.8 2.5 3.3 2.8 2.5 19.3 14.2 12.9 14.5 12.5 12.6 ns ns ns ns ns ns 3.7 3.1 2.9 2.5 8.3 6.4 5.6 5.1 17.6 12.6 11.0 9.7 3.3 2.8 2.5 2.2 18.1 13.1 11.7 10.5 ns ns ns ns 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 10 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter tdis disable time Conditions Min nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V CL = 10 pF; VCC(A) = 2.3 V to 2.7 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V CL = 10 pF; VCC(A) = 3.0 V to 3.6 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V CL = 15 pF; VCC(A) = 1.1 V to 1.3 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V [4] [3] [4] [3] [4] [3] [4] 25 C Typ[1] 7.2 6.0 6.3 5.2 Max 12.8 10.8 10.8 9.5 -40 C to +85 C Min 3.3 2.8 2.5 2.2 Max 13.4 11.4 11.5 10.1 Unit 3.7 3.1 2.9 2.5 ns ns ns ns 3.7 3.1 2.9 2.5 2.3 3.7 3.1 2.9 2.5 2.3 7.7 5.8 5.0 4.4 4.3 6.8 5.6 5.9 4.8 5.8 16.6 11.6 10.0 8.7 8.3 11.8 9.7 9.8 8.4 9.4 3.3 2.8 2.5 2.2 2.1 3.3 2.8 2.5 2.2 2.1 16.9 11.9 10.5 9.3 8.8 12.2 10.2 10.3 8.9 9.8 ns ns ns ns ns ns ns ns ns ns 3.7 3.1 2.9 2.5 2.3 3.7 3.1 2.9 2.5 2.3 7.4 5.5 4.7 4.1 3.9 6.6 5.4 5.7 4.6 5.6 16.1 11.1 9.5 8.3 7.8 11.3 9.3 9.4 8.0 9.0 3.3 2.8 2.5 2.2 2.1 3.3 2.8 2.5 2.2 2.1 16.5 11.5 10.1 8.8 8.3 11.7 9.7 9.8 8.5 9.4 ns ns ns ns ns ns ns ns ns ns 4.2 3.6 4.2 3.6 10.9 8.9 9.9 8.4 25.5 20.1 20.8 18.4 3.8 3.2 3.8 3.2 25.9 20.6 21.1 18.9 ns ns ns ns 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 11 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter CL = 15 pF; VCC(A) = 1.4 V to 1.6 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V CL = 15 pF; VCC(A) = 1.65 V to 1.95 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V CL = 15 pF; VCC(A) = 2.3 V to 2.7 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [4] [3] [4] [3] [4] [3] Conditions Min 25 C Typ[1] Max -40 C to +85 C Min Max Unit 4.2 3.6 3.1 4.2 3.6 3.1 9.7 7.6 6.8 8.9 7.4 8.0 20.8 15.3 13.6 16.0 13.7 14.1 3.8 3.2 2.7 3.8 3.2 2.7 21.4 16.1 14.5 16.6 14.4 14.8 ns ns ns ns ns ns 4.2 3.6 3.1 2.8 4.2 3.6 3.1 2.8 9.1 7.0 6.2 5.6 8.5 7.0 7.5 6.1 19.5 14.0 12.2 11.0 14.7 12.4 12.7 11.0 3.8 3.1 2.7 2.4 3.8 3.1 2.7 2.4 20.1 14.7 13.2 11.8 15.3 13.1 13.5 11.8 ns ns ns ns ns ns ns ns 4.2 3.6 3.1 2.8 2.5 4.2 3.6 3.1 2.8 2.5 8.5 6.4 5.6 4.9 4.8 8.0 6.6 7.1 5.7 7.1 18.4 13.0 11.2 10.0 9.6 13.6 11.3 11.7 10.0 11.5 3.8 3.2 2.7 2.5 2.3 3.8 3.2 2.7 2.5 2.3 18.8 13.5 11.9 10.6 10.1 14.0 11.8 12.3 10.5 11.9 ns ns ns ns ns ns ns ns ns ns 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 12 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter CL = 15 pF; VCC(A) = 3.0 V to 3.6 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V CL = 30 pF; VCC(A) = 1.1 V to 1.3 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V CL = 30 pF; VCC(A) = 1.4 V to 1.6 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V CL = 30 pF; VCC(A) = 1.65 V to 1.95 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V [3] [4] [3] [4] [3] [4] [3] Conditions Min 25 C Typ[1] Max -40 C to +85 C Min Max Unit 4.2 3.6 3.1 2.8 2.5 4.2 3.6 3.1 2.8 2.5 8.2 6.1 5.2 4.6 4.4 7.8 6.3 6.9 5.5 6.8 18.0 12.5 10.7 9.5 9.1 13.2 10.9 11.3 9.5 11.0 3.8 3.2 2.7 2.5 2.3 3.8 3.2 2.7 2.5 2.3 18.4 13.0 11.5 10.1 9.6 13.6 11.4 11.8 10.0 11.5 ns ns ns ns ns ns ns ns ns ns 5.1 4.3 5.1 4.3 13.8 11.2 13.9 11.7 33.1 26.1 28.5 25.4 4.6 3.8 4.6 3.8 33.8 27.7 29.2 26.2 ns ns ns ns 5.1 4.3 4.0 5.1 4.3 4.0 12.1 9.5 8.5 12.6 10.4 11.6 26.6 19.6 17.7 22.0 18.9 20.1 4.6 3.8 3.5 4.6 3.8 3.5 27.5 21.4 19.2 22.9 19.9 21.2 ns ns ns ns ns ns 5.1 4.3 4.0 3.4 11.4 8.7 7.7 7.1 24.8 17.8 15.9 14.3 4.6 3.8 3.5 3.1 25.6 19.5 17.3 15.3 ns ns ns ns 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 13 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter tdis disable time Conditions Min nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V CL = 30 pF; VCC(A) = 2.3 V to 2.7 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V CL = 30 pF; VCC(A) = 3.0 V to 3.6 V ten enable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time nOE to 2Y; see Figure 4 VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [4] [3] [4] [3] [4] 25 C Typ[1] 12.0 9.9 11.1 8.7 Max 20.2 17.1 18.3 15.5 -40 C to +85 C Min 4.6 3.8 3.5 3.2 Max 21.0 18.0 19.3 16.4 Unit 5.1 4.3 4.0 3.4 ns ns ns ns 5.1 4.3 4.0 3.4 3.3 5.1 4.3 4.0 3.4 3.3 10.6 7.9 6.9 6.2 6.1 11.5 9.3 10.5 8.2 10.7 23.3 16.4 14.4 12.8 12.4 18.7 15.6 16.8 14.0 17.0 4.6 3.8 3.5 3.2 3.1 4.6 3.8 3.5 3.2 3.1 23.9 17.8 15.6 13.6 13.0 19.3 16.3 17.5 14.7 17.6 ns ns ns ns ns ns ns ns ns ns 5.1 4.3 4.0 3.4 3.3 5.1 4.3 4.0 3.4 3.3 10.2 7.6 6.6 5.8 5.6 11.2 9.1 10.2 7.9 10.5 22.9 15.9 14.0 12.4 12.0 18.3 15.2 16.4 13.6 16.5 4.6 3.8 3.5 3.2 3.1 4.6 3.8 3.5 3.2 3.1 23.4 17.2 15.1 13.1 12.5 18.8 15.8 17.0 14.2 17.1 ns ns ns ns ns ns ns ns ns ns 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 14 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter CL = 5 pF, 10 pF, 15 pF and 30 pF CPD power dissipation capacitance output 2Y; fi = 1 MHz; VI = 0 V to VCC VCC(A) = VCC(B) = 1.2 V VCC(A) = VCC(B) = 1.5 V VCC(A) = VCC(B) = 1.8 V VCC(A) = VCC(B) = 2.5 V VCC(A) = VCC(B) = 3.3 V [1] [2] [3] [4] [5] All typical values are measured at nominal VCC(A) and VCC(B). tpd is the same as tPLH and tPHL. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs. [5] Conditions Min 25 C Typ[1] Max -40 C to +85 C Min Max Unit - 2.8 3.0 3.0 3.6 4.1 - - - pF pF pF pF pF 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 15 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 12. Waveforms VI nOE input GND tPLH VOH 1Y output VOL VM VM tPHL VM VM VI A input GND tPLH VOH 2Y output VOL 001aaj295 VM VM tPHL VM VM Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 3. Input nOE to output 1Y and A to output 2Y propagation delay times 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 16 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state VI nOE input GND tPLZ VCCO 2Y output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH 2Y output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aaj296 VM tPZL VM VX tPZH VY VM Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. VCCO is the supply voltage associated with the output pin. Output 1Y has no external load. Fig 4. Table 9. Enable and disable times Measurement points Input[1] VM 0.5VCCI 0.5VCCI 0.5VCCI Output[2] VM 0.5VCCO 0.5VCCO 0.5VCCO VX VOL + 0.1 V VOL + 0.15 V VOL + 0.3 V VY VOH - 0.1 V VOH - 0.15 V VOH - 0.3 V Supply voltage VCC(A), VCC(B) 1.1 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 17 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state VCC VEXT 5 k G VI VO DUT RT CL RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 5. Table 10. Load circuit for switching times Test data Load[2] tr = tf 3.0 ns CL 5 pF, 10 pF, 15 pF and 30 pF RL [3] Supply voltage Input VCC(A), VCC(B) 1.1 V to 3.6 V [1] [2] [3] [4] VEXT tPLH, tPHL tPZH, tPHZ open GND tPZL, tPLZ[4] 2VCCO 5 k or 1 M VI[1] VCCI VCCI is the supply voltage associated with the data input port. For measuring enable and disable times, CL and RL are connected to pin 2Y. Pin 1Y has no load. For measuring enable and disable times RL = 5 k, for measuring propagation delays RL = 1 M. VCCO is the supply voltage associated with the output port. 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 18 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 13. Transfer characteristics Table 11. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5. Symbol VT+ Parameter positive-going threshold voltage Conditions Min nOE inputs; see Figure 6 and Figure 7 VCC(A) = 1.1 V VCC(A) = 1.4 V VCC(A) = 1.65 V VCC(A) = 2.3 V VCC(A) = 3.0 V VT- negative-going threshold voltage nOE inputs; see Figure 6 and Figure 7 VCC(A) = 1.1 V VCC(A) = 1.4 V VCC(A) = 1.65 V VCC(A) = 2.3 V VCC(A) = 3.0 V VH hysteresis voltage nOE inputs; (VT+ - VT-); see Figure 6, Figure 7, Figure 8 and Figure 9 VCC(A) = 1.1 V VCC(A) = 1.4 V VCC(A) = 1.65 V VCC(A) = 2.3 V VCC(A) = 3.0 V 0.08 0.18 0.27 0.53 0.79 0.46 0.56 0.66 0.92 1.31 0.08 0.18 0.27 0.53 0.79 0.46 0.56 0.66 0.92 1.31 V V V V V 0.26 0.39 0.47 0.69 0.88 0.65 0.75 0.84 1.04 1.24 0.26 0.39 0.47 0.69 0.88 0.65 0.75 0.84 1.04 1.24 V V V V V 0.53 0.74 0.91 1.37 1.88 0.90 1.11 1.29 1.77 2.29 0.53 0.74 0.91 1.37 1.88 0.90 1.11 1.29 1.77 2.29 V V V V V 25 C Typ Max -40 C to +85 C Min Max Unit 14. Waveforms transfer characteristics VO VT+ VI VT- VH VO VH VT- VT+ VI mna207 mna208 VT+ and VT- limits at 70 % and 20 %. Fig 6. Transfer characteristic Fig 7. Definition of VT+, VT- and VH 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 19 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 240 ICC (A) 160 001aad691 80 0 0 0.4 0.8 1.2 1.6 VI (V) 2.0 Fig 8. Typical transfer characteristics; VCC(A) = 1.8 V 1200 ICC (A) 800 001aad692 400 0 0 1.0 2.0 VI (V) 3.0 Fig 9. Typical transfer characteristics; VCC(A) = 3.0 V 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 20 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 15. Package outline XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4x L (2) L1 e 8 e1 7 e1 6 e1 5 8x (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 10. Package outline SOT833-1 (XSON8) 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 21 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 16. Abbreviations Table 12. Acronym CDM CMOS DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 17. Revision history Table 13. Revision history Release date 20090120 Data sheet status Product data sheet Change notice Supersedes Document ID 74AUP1T1326_1 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 22 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP1T1326_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 20 January 2009 23 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer characteristics. . . . . . . . . . . . . . . . . . 19 Waveforms transfer characteristics . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 January 2009 Document identifier: 74AUP1T1326_1 |
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